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Solarflare and LDA Hit 120ns CME Tick-to-Trade Latency

Traders Magazine Online News, May 15, 2018

John D'Antona Jr.

Solarflare and LDA Technologies, partners who recently achieved a world-record 98-nanosecond tick-to-trade network latency based on the I/O in a STAC-T0 benchmark, are still working on latency.

The two companies announced the CME (Chicago Mercantile Exchange) Tick-To-Trade Solution and Xilinx MPSoC-based Generic Risk Check Framework, both providing nanosecond latency to traders integrating the products into their environments.

“These new products represent two milestones for the industry,” said Vahan Sardaryan, Co-Founder of LDA Technologies. “Significantly lower latency than competitive Tick-to-Trade FPGA solutions, and an efficient way to migrate Risk Checking software to nanosecond FPGA performance.” 

According to Ahmet Houssein, Vice President of Marketing at Solarflare, “Electronic trading environments include a variety of software components that can be accelerated with FPGAs using technology from Solarflare and LDA. Traders can expect more solutions based on our partnership in the near future.”

LDA Technologies CME Tick-To-Trade Solution

The CME Tick-To-Trade Solution incorporates the record-breaking LightSpeed TCP Offload Engine, an ultra-low latency CME MDP3 feed handler with A/B line arbitration, and an order triggering system. The solution allows customers to present a broad range of conditions which trigger FIX messages to be sent to the exchange. The actionable tick-to-trade latencies (as defined by the STAC-T0™ framework) are as low as 120-300ns depending on the triggering of specific conditions. In addition to automatic triggering, the FPGA-accelerated FIX gateway provides significant latency improvement to the software components of the trading systems.

LDA Technologies Risk Check Framework

The Risk Check Framework executes on FPGA boards with multiprocessor system-on-chips (MPSoCs) from various LDA partners. Both Send and Receive TCP Offload Engines, as well as the processor-to-FPGA two-way interconnect, are all included in the framework. The total base latency introduced by the framework is only 180ns which allows wire-to-wire latency as low as 300-400ns on most stock market binary protocols with moderately complex risk computation algorithms. The API provided will enable customers to quickly implement their risk check logic on a CPU with instant compile times and extensive debug tools, making this an open, software-driven solution.




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